The default TCP window size is 64 kbytes. This value is not sufficient to achieve 100 percent utilization in a WAN. For this analysis, the maximum window size has been scaled [5] to take into account the link rate and propagation delay of the links. Accordingly, the window size has been set to the bandwidth delay product:
TCP Window = RTT x Link Rate
The TCP segment size is 1536 bytes. The TCP model includes a small random delay which eliminates the phasing effects reported in [6]. The TCP model used in the simulations does not implement selective acknowledgment and processes acknowledgments without delay.
The Edge Switch Model -- As mentioned earlier, the edge switch model implements sophisticated traffic management features. The edge switch model supports per-VC queuing, and the buffer capacity is limited to 10,000 cells for all simulations. When the buffer occupancy grows above 90 percent capacity (9000 cells), per-VC thresholds are calculated to determine the fair share for each connection. Only connections using more than their fair share (equal share of the buffer) when the edge switch is congested experience packet discard. This congestion control mechanism ensures fairness among connections at the network edge.
UBR VCCs are aggregated onto a UBR or ABR VPC at the edge switch. UBR connections are scheduled onto the VPC using round robin arbitration. Therefore, the VPC contains a mix of cells from all active connections.
The edge switch also supports the ER ABR model, including VS/VD [2, 3]. UBR VCCs are aggregated onto an ABR VPC which is shaped according to the ER received in the backward VPC RM cells. See Table 1 for a complete listing of ABR parameters and values. UBR VPCs are shaped at PCR, which is set to the link rate in the simulation.
The Core Switch Model -- The core switches are modeled as simple FIFO queues with a given buffer size. When the network core supports ABR VPCs, the core switches perform ER ABR according to the Uniform Tracking (UT) algorithm [7]. The UT algorithm performs rate monitoring to adjust the ER value in the backward RM cells. The ABR sources at the edge switches shape the ABR VPCs according to the ER value. Because per-VC frame delineation is not visible by a core VPC switch, only cell discard is supported.
Performance Metrics
The following performance measures are considered in this analysis:
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Buffer occupancy
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Goodput
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Fairness
In the case of a rate-based control mechanism, buffer occupancy together with link utilization is an essential metric to evaluate. If at any point in time, the buffer occupancy is very high, this will mean that the control mechanism is accepting more cells into the network than it should. However, if the link utilization is low in the case when sources are active, this will mean that the control mechanism is overreacting. The fairness and goodput concepts are explained below.
Fairness Index -- One of the performance objectives is to provide fairness to all users of a network. Fairness ensures that no connections are arbitrarily discriminated against and no set of connections arbitrarily favored. A fairness index is defined in ATM Forum Traffic Management Specification version 4.0 [2] to evaluate how fairly the available bandwidth is distributed among the users. The fairness index is
where n is the number of connections (or sources) sharing the network resources, and xi is the ratio of the actual throughput of connection i to the optimal throughput. The optimal throughput is the fair share of the available bandwidth for the considered connection.
For the configuration in Fig. 3, all the contending connections are statistically equivalent and the optimal throughput is the same for all the connections.
Goodput -- Goodput is defined as the ratio of achieved throughput to maximum achievable throughput. Throughput is defined as the rate of good data received by the TCP receiver. Good data refers to the amount of packets successfully received by the TCP receiver. Retransmissions triggered by the TCP stack or duplicate packets received at the receiver are not counted as good data.
The maximum achievable throughput is limited by the bottleneck in the network or at the source. Usually, goodput is expressed as a percentage of the bottleneck link and reflects the efficiency in using the link.
The goodput is then given by
where GD is the total amount in bits of data corresponding to successfully transmitted packets (good data), T is the measurement period (simulation time in this case), LR is the maximum transmission rate of the bottleneck link between the two switches (line rate), and 
is the AAL5 inefficiency.
Simulation Results
The ER algorithm implemented in the core switch has a configurable target rate parameter. The target rate was set to utilize 90 percent of the output core switch. In this analysis, the ABR goodput is calculated relative to the target utilization.
The TCP window size is set to the bandwidth delay product (BDP) , as shown in Table 2. The core switch buffer sizes have been rounded up to multiples of 10,000-cell values.
Goodput Performance -- One approach to compare the scalability of UBR and ABR VPCs is to compare the goodput as the delay increases for a given buffer size. In this case, the core switch buffer size is limited to 10,000 cells. Figure 5 shows that ABR VPCs are able to maintain a high level of goodput across all RTTs. The core switches experience low average cell occupancy, and congestion is successfully pushed to the edge switches where intelligent packet discard is supported. By distributing congestion across the edge switches, the ABR VPC network maintains high performance.
UBR VPC performance is significantly affected by increasing delay. In the UBR VPC case, the core switch buffer is the single point of cell loss with 20 connections bottlenecked, and regularly experiences random cell loss. In the ABR VPC case, congestion occurs at the edge switches where only four connections are bottlenecked. It is well known that TCP requires packet discard to maximize performance [1]. Once a single cell is discarded from a packet, the packet will be discarded at the TCP receiver. Transporting partial packets to a receiver is a waste of bandwidth.
Random cell loss causes many packets from many connections to be discarded and increases the number of TCP timeouts. As more connections experience timeouts at the same time, bandwidth becomes underutilized. Simulation results show that many more timeouts are experienced with UBR than ABR, up to four times more. The core switch buffer is not large enough to keep the output link utilized while the TCP connections recover from congestion. The core switch output link utilization drops from 87 percent (RTT = 25 ms) to approximately 75 percent (RTTs of 50 and 100 ms).
The results show that an ABR VPC network core scales, and maintains high performance, with increasing network delays. This aspect of delay-insensitive performance is important in real networks since it demonstrates route-insensitive performance. That is, it ensures that users will see the same performance before and after reroutes.
Figure 6 shows the sensitivity of UBR VPC goodput performance to different core switch buffer sizes. Figure 6 shows that TCP goodput performance only improves marginally when there is more than approximately three times the BDP of buffering at the core switch. As the buffering increases, more sources are able to recover from congestion, and the total number of TCP timeouts decreases.
This analysis shows the core switch buffer requirements for UBR to achieve a comparable goodput performance to that of ABR. In this configuration, the required buffering is approximately three or four times the BDP (per output port).
Figure 7 compares the core switch buffer requirements for UBR VPCs to equal the goodput performance of ABR. Again, this shows that ABR scales much better than UBR as the RTT increases. As the delay increases, UBR requires larger and larger buffers to achieve high performance. However, ABR is able to dynamically control the core switch buffer occupancy and successfully move congestion to the edge switches. The intelligent packet discard ensures fairness, and ABR is able to maximize goodput performance.
Fairness -- Fairness can apply at the VPC and VCC levels in a hierarchical fashion. Table 3, Table 4, and Table 5 show the fairness performance of:
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ABR
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UBR with 10,000-cell core switch buffers
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UBR with core switch buffer size large enough to have goodput equal to ABR
Fairness for VPC 1, for example, measures the fairness among all connections within VPC 1. The overall VPC fairness measures the fairness among VPCs. The VCC overall fairness measures the fairness among all VCCs and may differ from the overall VPC fairness.
Tables 3–5 show that the functionality at the edge solution is able to ensure fairness at all levels. Because UBR experiences random cell loss, it is expected that it is somewhat fair. However, in all cases ABR fairness is equal to or better than that of UBR at the VPC and VCC levels.
Note that the fairness is not a linear function. The improvement required to raise the fairness performance increases as the fairness increases. For example, a large performance increase is required to increase fairness from 97 to 98 percent.
Discussion
The simulation results show that supporting ABR VPCs in the network core is a more scalable and efficient solution than UBR VPCs. The ABR VPC solution is able to minimize core buffer requirements while maintaining high goodput performance over varying delays. Large buffers in the core switches will add queuing delay to the traffic during congestion. By pushing congestion to the network edge, ABR is able to utilize intelligent packet discard to ensure fairness at the VCC level. Furthermore, pushing congestion to the edges allows for more efficient use of the available buffers at the edge switches than UBR VPCs.
Summary
Functionality at the edge provides the advantage of allowing the consolidation of non-real-time traffic into ABR VPCs to provide scalable networks, maximal bandwidth usage, ease of manageability, and reduced core switch resource requirements.
The hierarchical nature of the proposed design provides the flexibility, performance, and scalability required from a multiservice broadband network.
Flexibility -- The design can accommodate a wide range of non-real-time services, be they native ATM services or legacy services with ATM adaptation at the edge of the network.
Scalability -- The design scales well given the consolidation of services at the edge of the network and its management simplicity in the core. Supporting ABR VPCs for all non-real-time traffic further reduces the number of VPCs in the network core.
Performance -- The network performance and end-to-end performance are achieved by keeping a congestion-free core and moving the complexity associated with managing the resources for the specific services to the edge of the network.
Efficiency -- The ABR VPC dynamically adjusts the VPC shaping rate to utilize bandwidth made available by real-time VPCs with static bandwidth allocation. In this manner, the network core capacity is maximized.
Simulation results show that ABR VPCs are successful in pushing congestion to the network edge where per-VC intelligent packet discard is able to maximize performance. The results show that ABR is a scalable solution to maximize bandwidth in the network core while providing fairness at the VPC and VCC levels.
References
[1] Romanow and S. Floyd, "Dynamics of TCP Traffic over ATM Networks," IEEE JSAC, vol. 13, no. 4, May 1995, pp. 633–41.
[2] ATM Forum, ATM Forum Traffic Management Specification, v. 4.0, AF-TM-0056, Apr. 1996.
[3] ITU-T Rec. I.371, "Traffic Control and Congestion Control in B-ISDN," SG 13, Geneva, Switzerland, Nov. 1995.
[4] W. R. Stevens, TCP/IP Illustrated, Vol. 1, The Protocols, Addison-Wesley, 1994.
[5] V. Jacobson, R. Braden, and D. Borman, "TCP Extensions for High Performance," RFC 1323, May 1992.
[6] S. Floyd and V. Jacobson, "On Traffic Phase Effects in Packet-Switched Gateways," Internetworking: Res. and Experience, vol. 3 no. 3, Sept. 1992, pp. 115–56.
[7] C. Fulton, S. Li, and C. S. Lim, "UT: ABR Feedback Control with Tracking," ATM Forum 97-0239 -- Traffic Management, 1997.
[8] ATM Forum, "Addendum to Traffic Management V4.0 for ABR Parameter Negotiation," AF-TM-077.000, Jan. 1997.
Biographies
Steve Rosenberg is a member of the Advanced Technology Support group at Newbridge Networks Corporation. He joined Newbridge as a member of the ATM performance and traffic management group in 1995. He holds a B.Eng. in electrical engineering from Carleton University in Ottawa, Canada.
Mustapha Aissaoui is manager of the Advanced Technology Support group at Newbridge Networks Corporation. He holds an electrical engineering diploma from Polytechnic School of Algiers and a M.Sc. in electrical engineering from the University of Ottawa. He joined Newbridge in 1993 as a member of the ATM Network Engineering group.
Keith Galway is a product planner of ATM products for Newbridge Networks Corporation. He joined Newbridge in 1988 as a hardware designer before moving to his current role in 1997. He holds a B.Sc. in electrical engineering from the University of Waterloo.
Natalie Giroux is director of Performance Engineering for Newbridge Networks Corporation. She joined Newbridge as manager of the ATM performance and traffic management group in 1993. She has chaired the Traffic Management working group at the ATM Forum since February 1994. She holds an M.Sc in computer simulation from Université Laval, Quebec City, Canada. Prior to joining Newbridge, she worked as a teletraffic performance analyst for Bell-Northern Research in Nepean, Canada.
