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This article was published in the June 1998 issue of
IEEE Personal Communications.

ABSTRACT

 

The radio frequency portion of a handheld wireless communications device represents a significant fraction of the battery drain of the overall unit. As a result, an intensive effort is underway on a worldwide basis to minimize the overall radio frequency power requirements. This effort has proceeded on many fronts, with the best work drawing on the multidisciplinary efforts of researchers in the communications systems, circuit design, and semiconductor technology areas. This article will summarize the significant technological challenges to the realization of low-power radio frequency circuits, and will follow with a discussion of the research programs that have been put in place to address these challenges.

 

 

Radio Frequency Integrated Circuit Technology for Low-Power Wireless Communications

 

Lawrence E. Larson
University of California - San Diego

 

A wireless radio frequency receiver typically finds itself immersed in a sea of unwanted and potentially interfering signals -- from cellular base stations to television transmitters, airport radars, and so on -- and from that sea is able to pick out the unique desired signal, and reproduce and amplify it with near perfect fidelity. This incredible feat of modern engineering is often taken for granted by the user of the device, but represents nearly a century of accumulated engineering expertise and relentless refinement.
The use of these devices for portable applications introduces another dimension of performance requirements, ultra-low-power. Now the radio frequency device must operate from low-voltage batteries of limited energy densities and variable voltage. The ideal radio communicator would dissipate virtually no power, allowing for months or even years between recharges. These handheld devices are composed of a combination of digital, mixed-signal, and radio frequency circuits that together perform all of the functionality required to communicate with great fidelity across the hostile wireless environment.
Digital integrated circuits have been able to make astonishing strides in lowering power dissipation due to their increasing levels of integration and lower power supply voltage operation. These improvements, in turn, are the result of ever smaller geometries and improved integrated circuit technology, as well as the increasing scales of return involved with Moore's Law [1]. Similar dramatic improvements have been made recently in the implementation of radio frequency circuits for wireless communications, and these results derive from a complex combination of integrated circuit technology, semiconductor material, circuit design, and architectural improvements. It is generally acknowledged that the best way to achieve the lowest-power performance from next-generation wireless transceivers is to perform a high degree of signal processing in the digital complementary metal oxide (CMOS) domain, with the remaining analog/RF circuitry required to interface the antenna to the digital signal processor (DSP). There is an optimum boundary between analog and digital processing in a receiver, which depends on the frequencies, performance requirements, and available technologies. System implementations with a high degree of flexibility may not be very power-efficient, and vice versa. In order to understand the prospects for further improvements in this area, an understanding of the technical problems involved in radio transceiver design is required.
For example, a typical analog cellular telephone signal (AMPS in the United States) has a carrier frequency of roughly 870 MHz, but the signal frequency itself occupies less than 30 kHz. The receiver must therefore select this 30 kHz signal from all the other cellular signals, which occupy approximately 25 MHz, and all the other competing signals in the environment, which can occupy nearly 500 MHz of bandwidth. So the difference in frequency ranges between the desired signal and potentially interfering undesired signals is less than 10–3. The receiver circuit must be very selective indeed! In addition, the desired signal received at the antenna is often significantly weaker than the undesired signals, resulting in interference and cross-modulation of the interfering signal with the desired signal.
Similar challenges exist for a wireless transmitter, which is required to transmit a signal of high precision and spectral purity, over a relatively narrow bandwidth. FCC and other regulatory body limitations prohibit significant spectral "spill-over" due to nonlinearities in the transmitter, since out-of-band transmitted power levels are strictly limited in order to avoid potential interference with nearby systems. As a result, the art of transmitter design is at least as complicated as that of the receiver.
The modern challenge of radio transceiver design is to continue to reduce the power dissipation required by these devices, while at the same time lowering their cost and raising their operating frequency and performance. In addition, modern digital communications techniques require greater sophistication in the design and implementation of the radio itself, since improved digital modulation techniques that offer greater bandwidth efficiency require improved performance from the radio portion of the system.
This article will begin with a discussion of RF transceiver architectures, and then follow with a brief overview of fundamental limitations on transceiver performance. It will then discuss possible strategies for lower-power operation of these devices.

An Overview of Radio Frequency Architectures and Requirements for Wireless Communications

The superheterodyne receiver of Fig. 1 remains the architecture of choice for the vast majority of RF applications in the world today, and represents a good starting point for the analysis of power requirements in receiver architectures in general. It originated with Edwin Armstrong during World War I, and the word "heterodyne" is derived from the Greek words "heteros," meaning different, and "dynamis," meaning power [2]. Its perennial popularity is due to its ability to reproducibly pick out narrow-bandwidth high-frequency signals from the surrounding background clutter of signals outside the frequency range of interest.
In this design, the radio signal is sent from the receiving antenna to a low-noise amplifier (LNA), whose purpose is to boost the signal level without reducing the signal-to-noise ratio significantly. The signal level at the antenna can range between 1 ΅V rms to nearly 100 mV rms -- over 100 dB variation! At the low end of the signal range, the LNA performance is fundamentally limited by thermodynamic issues, while at the high end of the signal range the challenge is to minimize the effects of nonlinearities on receiver performance. These diverse requirements are often referred to as the "LNA bottleneck" [3]. As a result, the high-frequency LNA must exhibit excellent performance over both small-signal and large-signal conditions.
In addition, the LNA is typically "on" all the time -- listening for transmitted signals of interest -- so it is constantly draining battery power while the unit is in operation. The combination of extremely high performance and low power requirements result in the LNA being one of the most significant power drains in the system. The next section will highlight some of the fundamental technological limitations of LNA performance.
Following the LNA, the signal is typically passed through a mixer, which essentially multiplies the input signal (frf) by a local oscillator signal of constant frequency (flo), producing an output signal whose frequency is the frequency difference between the two inputs (flo – frf) -- the so-called intermediate frequency (IF) -- and whose amplitude is proportional to the original input signal. Preceding the mixer, an analog filter eliminates the response to an undesired input signal at (2flo – frf) that would also down-convert to the intermediate frequency. This image reject filter is typically implemented with a physically large surface acoustic wave (SAW) filter. In addition to their size, these filters have extremely unforgiving sensitivities to variations in source impedance, ground loops, and so on. The dilemma of image rejection and its elimination in heterodyne receivers is one of the fundamental limitations on performance and power reduction in RF systems.
A second limitation of traditional frequency-translating mixers and the heterodyne architecture is their sensitivity to a menagerie of spurious responses that result from nonlinearities in the amplifiers preceding the mixer, as well as the mixer itself. These nonlinearities produce harmonics of the input and local oscillator frequencies that can themselves mix down to the IF frequency. In this case, the "input" consists of the desired frequency as well as other signals within the desired band, and potential "jamming" signals form other undesirable sources. In cases such as this, nflo – mfrf = ±IF, where n and m are integers; the potential range of frequencies where this unfortunate set of circumstances can occur is nearly limitless. So a variety of harmonics of the desired frequency as well as the local oscillator can intermix to create a spurious response at the IF, which is indistinguishable from the desired signal.
As a representative example of a superheterodyne transceiver, let's examine the typical architecture for a digital cellular handset (IS-54/IS-136), whose simplified block diagram is shown in Fig. 2 [4]. The IS-54/136 standard represents a first-generation digital cellular standard, and is a good example of a typical "high-tier personal communication services (PCS)" application [5]. Other examples of high-tier PCS include IS-95, Global System for Mobile Communications (GSM), and DCS-1800. The transmitter portion of the RF unit operates from 824–849 MHz, and the receiver portion operates from 869–894 MHz, which are the standard frequencies for operation in the United States.
Based on considerations of cell size, transmitter power, expected path loss, and bandwidth, the total receiver noise-figure (NF) requirements are typically 6 dB or lower. The receiver NF is defined as the ratio of the signal-to-noise ratio at the input to the signal-to-noise ratio at the output -- a ratio of ratios. It is ideally unity (or 0 dB), and overall system performance is degraded as its value rises from unity. At the same time, the received in-band signal power can vary from roughly 0.1 pW to 10 ΅W, so the dynamic range requirements of the receiver are very challenging indeed. Out-of-band interferers from a variety of potential sources can raise the received power to even higher levels; hence the need for a sharp band-pass filter from 869–894 MHz to minimize out-of-band interference.
The transmitted power from the handset power amplifier can rise as high as 200 mW, although the power amplifier is typically designed for a peak power of 1 W or even higher, and then "backed off" by 7 dB in order to maintain the required linearity. A high-Q bandpass filter is provided at the output in order to conform to FCC requirements on out-of-band radiated emission. Spurious performance is typically required to be 60 dB below the carrier in this system. The power amplifier will ideally maintain a high gain, linearity, and power-added efficiency over the entire bandwidth and output power range when operated from a 2.7 V battery power supply.
The frequency synthesizer produces the local oscillator for upconversion/downconversion, and is typically produced by a low phase-noise voltage-controlled oscillator (VCO) that is locked to a lower frequency crystal reference. The phase noise of the VCO is a crucial parameter, because channel–channel spacing is only 30 kHz in this system, and mixing of adjacent channels into the desired band by the noise of the oscillator (so-called reciprocal mixing) can significantly degrade the received carrier/noise (C/N) performance. In addition, the sidebands of the VCO phase noise add directly to the noise floor in the system passband, further degrading the C/N [6]. A typical requirement is that the C/N be at least 7 dB for a bit error rate of 10–3. This in turn requires that the oscillator phase noise be at least –100 dBc/Hz at 100 kHz from the center frequency. Phase noise issues in local oscillators will be discussed further in the next section.
This example shows the use of a standard superheterodyne receiver for a current-generation digital cellular application. Its popularity is a result of its relative insensitivity to component variations and immunity to low-frequency anomalies and self-oscillation problems. However, the architecture of the superheterodyne receiver also has a number of problems, which make it very poorly suited for completely monolithic integration -- the key to lower power operation. The major problems are the ubiquitous image and spurious responses, which must be carefully controlled through bulky and expensive off-chip filters. These filters represent the major impediment to raising the level of integration of wireless radios, since they cannot easily be implemented monolithically. Therefore, alternative architectures that do not suffer from these limitations are actively being explored.
One example of a potential improvement in the area of receiver architectures is the use of quadrature signal processing techniques (also known as the Hartley phasing method) as a way of eliminating some of the image rejection filtering. In this case, the image rejection problem is solved geometrically through the use of two local oscillators and mixers, operated at 90s phase shift with respect to each other. Figure 3 is a block diagram of a typical image rejection mixer using the Hartley phasing approach. After downconversion, the two paths are again shifted 90s with respect to each other to produce the desired downconverted response.
Summing or subtracting the resulting signal can produce either the desired signal or the image. In this particular approach, the need for an image rejection filter is eliminated, but the image rejection of the system is highly dependent on the accuracy of the phase shift and the gain matching in the two legs of the downconverter [7]. Image rejection in excess of 60 dB requires a phase accuracy of less than 0.5s, which is very difficult to realize on a monolithic integrated circuit.
Substantial progress has been made recently in the area of direct downconversion -- or homodyne -- approaches for wireless receivers, which also eliminate the need for image rejection filters, and are better suited to monolithic integration. A schematic diagram of a typical direct conversion receiver is shown in Fig. 4. An excellent review of recent research in this field is presented in [8, 9]. In this case, the intermediate frequency (IF) is at dc, and the in-phase and quadrature (I and Q) paths of the mixer contain the positive and negative frequency components of the desired signal. The advantages of this particular architecture are that it is uniquely well suited to monolithic integration, due to its lack of complex filtering, and its intrinsically simple architecture.
However, although it is being actively researched, the direct conversion receiver has not gained widespread acceptance to date, especially in high-performance wireless receivers, due to its intrinsic sensitivity to dc offset problems, even-order harmonics of the input signal that interfere with the desired signal, and local-oscillator leakage problems back to the antenna. These issues are all being actively pursued by a variety of worldwide research groups, and it is anticipated that they will gradually be solved with further design maturity.
These basic downconversion approaches -- heterodyne and homodyne -- can be combined in different creative ways to optimize performance and power dissipation. For example, an interesting variation on the superheterodyne/homodyne receiver architecture is the "wideband IF double conversion" (WBIFDC) technique recently promoted by researchers at the University of California-Berkeley [10]. In this case, a low-IF image reject downconverter operating at a fixed local oscillator frequency is followed by a second stage of direct downconversion, whose frequency is set by a tunable oscillator. This is essentially a dual downconversion heterodyne receiver, where the first downconversion employs an image reject mixer, and the second the homodyne approach. An example is shown in Fig. 5.
The advantages of this architecture are that it eases the generation of the first local oscillator, which is now at a fixed frequency, and that reradiation of the local oscillator back to the antenna is not a problem, as it would be if a direct downconversion technique were employed. This approach is highly desirable for monolithic integration, but suffers from the use of six mixers to perform the complete downconversion, raising the dc power dissipation considerably. It also suffers from the same problem of existing homodyne receivers in terms of sensitivity to dc offsets and second-order distortion.

Fundamental Limitations on Low-Power Operation for Wireless Transceivers

Because of their multidimensional requirements and essentially analog nature, it is difficult to establish fundamental performance vs. power trade-offs for RF transceivers in a manner analogous to CMOS digital integrated circuits [11] or analog switched-capacitor circuits [12]. Instead, the best approach is to examine each of the important circuit blocks for performance trade-offs, especially in the critical areas of the low-noise and power amplifiers, and then combine these results with new architectures to realize overall improvements in power dissipation. In that spirit, this section will summarize the fundamental limitations on LNA and power amplifier performance, especially for the realization of ultra-low-power RF transceivers.

Relationship between Integrated Circuit Technology and Radio Frequency Performance/Power Dissipation

As with CMOS digital integrated circuits, the relentless progress of integrated circuit technology has had a profound impact on the performance and functionality of RF devices. Reducing the gate length of a FET -- allowing more devices to be placed on an integrated circuit die -- also improves the transistor speed, allowing it to achieve high gains at higher frequencies.
The standard figure of merit for high-frequency transistor performance is the fT -- the frequency of unity short-circuit power gain. The fT of the device is inversely related to transistor gate length, so it has improved dramatically in recent years as photolithography has continued to improve. The fT of the device is also related to the velocity of electrons as they travel through the device, so improved semiconductor materials like GaAs and InP offer even higher performance for a given gate length. Unfortunately, production lithographic processes for these more advanced technologies are usually a generation or two behind silicon, making the speeds of production devices roughly comparable.
In general, the fT of the device must be at least five times the desired frequency of operation in order for the resulting circuit to have acceptable performance. Until recently, the level of performance necessary for the realization of wireless components was not achievable by silicon technology, and instead had to be implemented with more expensive GaAs technology. However, as the graph of Fig. 6 shows, the performance of silicon bipolar, and now MOS, devices has improved so much that mainstream silicon digital integrated circuit technology is now able to address the requirements of the wireless transceiver.
A second important transistor figure of merit is fMAX, the frequency of unity power gain. This frequency is usually slightly larger than the fT of the device, and represents the maximum frequency where the transistor can exhibit any gain whatsoever. The two figures of merit are closely related, so it is usually sufficient to consider the fT when assessing the relative merits of technologies for wireless applications.
Another key figure of merit for a transistor amplifier is the level of distortion it produces as a result of the nonlinearities within the transistors themselves. Nonlinearities in transistor amplifiers represent an upper limit on input signals in the same way that the transistor noise figure imposes a lower limit on input signals. The ratio of the upper and lower limits on signal level for a given signal-to-noise-ratio is referred to as the dynamic range of the amplifier, and is another key component of RF receiver performance.
Cubic nonlinearities in amplifier performance can be especially devastating to receiver performance, since the intermodulation of two signals at frequencies 1 and 2 due to nonlinearity create a new distortion product at (21 – 2) and (22 – 1). These spurious signals, which appear at a frequency very close to the original inputs, are impossible to filter out, and rise in amplitude much faster than the desired output as the input signals rise.
Nonlinearities of this type are affected by fundamental transistor limitations, but can also be partially alleviated by improved circuit design approaches -- an area of very active research in the circuit design community today (see especially [13]). Therefore, it is difficult to precisely determine the upper limit on amplifier linearity, and hence establish a tradeoff between linearity and power dissipation. However, an absolute upper limit on signal swing at the input of an amplifier is usually determined by the power supply voltage itself. Hence, the trend toward lower power supply voltages for digital applications presents a significant challenge to receiver designers as they attempt to maintain receiver dynamic range while reducing power dissipation.

Fundamental Limits on Low-Noise Amplifiers

As mentioned before, LNAs are one of the key performance bottlenecks in an RF system. They are required to contend with a variety of signals coming from the antenna, often of larger amplitude than the desired signal, so both low noise and high linearity are required simultaneously. These requirements are often at odds with an additional requirement for low power dissipation.
LNAs are usually required to amplify a signal coming from the antenna whose lowest level is very close to the thermodynamic limit of background noise, given by kTB, where k is Boltzman's constant, T is the ambient temperature, and B is the bandwidth. In the case of a 50 kHz signal, this corresponds to a background noise power level of only 10–15 W! Thus, the intrinsic noise of the amplifier when connected to the antenna should not be much larger than the noise due to the antenna itself. The ratio of these two quantities is known as the NF of the amplifier.
A very simplified expression for a transistor minimum NF in an impedance matched circuit is given by [14]

where gm is the device transconductance, and rb/g is the base or gate resistance, depending on whether the device is a bipolar or field-effect transistor, and f is the frequency of operation.. This illustrates the importance of high transistor fT at low dc currents for handheld wireless applications. Unfortunately, a typical transistor's fT peaks at a relatively high current, so there is an inevitable trade-off between low-power operation and the best achievable NF in a given semiconductor technology. The higher the gain for a given power dissipation and NF, the better the performance.
Figure 7 plots amplifier bain/DC power dissipation (in dB/mW) as a function of NF (in dB) for a variety of reported LNAs in silicon and GaAs technology at 2 GHz. Most of the recently reported LNA results, fabricated in Si CMOS [15] or bipolar technologies [16, 17], fall along a gain/(Pdc*NF) line of approximately 0.4 (1/mW).
By comparison, a recent SiGe HBT result [18] demonstrated a fully integrated LNA with 0.95 dB NF, 2 mW power dissipation, and 10.5 dB gain at 2.4 GHz, for a figure of merit of approximately 5.5 (1/mW). The best reported GaAs LNAs have figures of merit of approximately 3.0 (1/mW) [19–21]. These results demonstrate the potential performance advantage of the relatively expensive GaAs or SiGe technologies at these frequencies where dc power dissipation is a major consideration. This comparison is slightly complicated by the fact that these circuits operate at different power supply voltages, and FET-based circuits tend to exhibit higher performance at high voltages than do bipolar transistor circuits.
Linearity is an equally important figure of merit for front-end transistor amplifiers. In this case, an often-used linearity figure-of-merit is the ratio of the input third order intercept point (IIP3) to the DC power dissipation. The IIP3 point occurs when the extrapolated intermodulation products are equal in magnitude to those of the desired output signal. Field effect transistors (MOSFETs as well as GaAs MESFETs and PHEMTs) generally exhibit improved third order intermodulation distortion compared with bipolar devices, due to their near square-law current vs. voltage behavior. On the other hand, bipolar transistor amplifiers have recently demonstrated outstanding linearity performance as well, apparently due to the cancellation of the resistive and capacitive nonlinearities in the base-emitter junction at certain frequencies [22]. As in the case of NF, the performance advantages of SiGe HBT and GaAs technologies becomes significant if dc power dissipation is a critical parameter, although the improvement is less dramatic. The best LNA results have a ratio of IIP3/DC power of approximately 0.15.

Fundamental Limits on Power Amplifiers

The complications associated with low-power operation of power amplifiers for RF applications are at least as challenging as those associated with LNAs. The power amplifier circuit must simultaneously satisfy requirements of linearity, gain, output power, and power-added efficiency. At the receiver input linearity is necessary in order to maintain the signal-to-noise ratio. At the transmitter output, maintaining linearity is important in order to avoid adjacent channel interference problems.
In addition, the trend toward lowered power supply voltages (from 5 V to 3 V and even lower) has made it difficult to maintain the required output power and efficiency from the power amplifier due to impedance matching limitations. Finally, the power amplifier must deliver a wide range of output powers to the antenna as the user moves throughout the cell site. Ideally, the power-added efficiency of the amplifier should not degrade significantly as the output power varies from near zero to its maximum value. Power-added efficiency is defined as the power delivered to the antenna divided by the sum of the dc power delivered to the device and the rf power delivered to the input. Ideally it should be 100 percent, but values of 30–50 percent are more common for typical cellular applications.
One of the major dilemmas in wireless systems is that power amplifiers are typically operated in a "backed-off" mode relative to their peak power and power-added efficiency points in order to meet the linearity requirements of the system. When an amplifier is operated in this regime its output power has dropped, but its dc power remains roughly the same. Hence, its power-added efficiency suffers considerably. The degree of back-off varies depending on the modulation scheme employed -- 0 dB for Gaussian multiple shift keying (GMSK) (GSM and DECT) , 7 dB for Pi/4DQPSK (IS-54 and PHS) , 10 dB for quadrature phase shift keying (QPSK) (IS-95), and 12 dB for 16-quadrature amplitude modulation (QAM) are typical. In this sense, constant envelope modulation schemes like GMSK have distinct advantages for power amplifier performance, since they can operate at near peak efficiency. However, there is a significant penalty paid with GMSK in terms of the spectral efficiency (in ((b/s)/Hz) compared with the other modulation approaches.
In digital communications systems the linearity requirement of the output power amplifier -- which determines the required back-off -- is usually specified as an adjacent channel power ratio (ACPR) in dBc, rather than the more traditional IP3/IP5 used in analog communications applications. ACPR is a measure of the spectral "spillover" due to amplifier nonlinearities into an adjacent frequency band by a digitally modulated waveform. A useful expression for the required IP3 in terms of specified ACPR for a CDMA system was recently derived [23], and is given by

where IP3 is the required output third order intercept point in dBm, B is half the signal bandwidth, f1 and f2 are the out-of-band frequency limits, Po is the output power of the amplifier, and PIM3(f1, f2)is the out-of-band specified power. This expression assumes that only third-order nonlinearities determine out-of-band power, although it can be used with some modifications for examining the effects of higher-order nonlinearities as well.
Power amplifiers are typically operated in the "class-AB" mode for most applications in an attempt to achieve a compromise between linearity and power-added efficiency. In this mode of operation the transistor is turned "off" for a brief period of time, improving its power efficiency but compromising its linearity and gain. In this case, the factors of key importance for amplifier performance are transistor fMAX (for high power gain), linearity (for lowest possible adjacent channel interference), and breakdown voltage. As it turns out, the breakdown voltage has become less critical for handsets in recent years, due to the reduction of operating voltages in most handheld units. The power-added efficiency of a power amplifier is given by the well-known expression

where is the collector/drain efficiency (which typically varies from 40–75 percent) and G is the amplifier gain. Since gain is so critical to achieving the best performance, most state-of-the-art power amplifiers have been implemented in GaAs technology to achieve the highest possible power-added efficiency. Figure 8 summarizes a recent comparison of monolithic power amplifier performance for PHS applications, where the adjacent channel leakage specification of –55 dBc is specified at 600 kHz from the carrier center [24].

Fundamental Limits on Voltage-Controlled Oscillators

The VCO that supplies the local oscillator signal for the transceiver represents one of the most vexing challenges in the area of low-power design. The ideal VCO output exhibits no phase noise, tunes over a fixed frequency range and is insensitive to temperature, process drift, output loading, or power supply variations. Nonmonolithic VCOs are available today that closely approximate this ideal and sell for fractions of a dollar in high volume [25]. They typically employ discrete silicon bipolar transistors, high-quality surface mount inductors, and varactor diodes, and are laser trimmed to the proper center frequency. Their power dissipation is relatively modest, but by no means ideal. By contrast, a completely monolithic integrated VCO suffers from low-quality monolithic inductors (typical Q-factors are less than 20), poor-quality varactor diodes, and an inability to trim the center frequency to accommodate its inevitable drift due to process variations.
Despite these drawbacks, substantial progress has recently been made in the development of completely monolithic silicon VCOs for wireless communications in the expectation that lower-power dc power dissipation will result from a completely monolithic implementation. Most of the work to date has focused on improved techniques for realizing high-Q monolithic inductors. These efforts include the use of thick gold metallization [26], multiple metal layers in parallel [27], bulk micromachining techniques for the removal of resistive material underneath the inductor [28], and spun-on thick dielectrics [29]. Peak values of monolithic inductor Q in the 5–20 range have been achieved to date, but this is still well below what is achievable using off-chip components, which have typical Qs in the 50–500 range.
The quality factor of the VCO resonator, which is mostly determined by the inductor, is especially important due to its effect on the phase noise of the resulting oscillator. A simplified expression for oscillator phase noise, which gives good agreement with experimental data over a broad range of oscillator circuits, was derived by Leeson [30]:

where S(m) is the output power spectral density at frequency m, S is the power spectral density of the oscillator input phase error (roughly 2NFkT/Ps, where NF is the noise figure and Ps the signal power), Q is the resonator quality factor, and o is the center frequency of the oscillator output.
This result illustrates the importance of the quality factor of the resonator circuit for an oscillator, since the phase noise drops as the square of the quality factor. Low-noise oscillators also require a high output amplitude and an LNA as the heart of the circuit in order to achieve the best performance. This requirement for a high output amplitude is once again in contradiction to the requirement for low dc power dissipation, and improved oscillator structures are being developed that operate from low power supply voltages and still maintain acceptable NFs.
The difference between the performance of VCOs with internal and external resonators is illustrated in Fig. 9. Generally, the best performance is obtained from circuits employing external resonators. However, it is expected that the performance of fully monolithic oscillators will continue to improve as various groups continue to develop improved techniques for inductor Q enhancement. It is also interesting to note that the dependence of oscillator performance on dc power dissipation is not particularly strong, indicating that good progress is being made in the area of low-power design for wireless applications.

Battery Considerations for Portable Wireless Devices

Modern-day battery technology represents a fundamental constraint on the lifetime of portable wireless communications devices. Whereas digital integrated circuit technology doubles in complexity every two years, and A/D converter technology doubles in performance roughly every eight years [31], battery technology doubles in energy density roughly every 35 years [32]. This trend has accelerated somewhat in recent years with improvements in battery technology spurred by the needs of portable electronic devices, but the rate of improvements is still well below that of typical microelectronics technology.
Typical considerations in battery use are the specific energy of the battery (in watt hours per kilogram), battery cell voltage (in volts), and lifetime (in number of cycles). The well-known nickel cadmium (NiCd) batteries have typical cell voltages of 1.25 V and specific energies of 60 Whr/kg. Lithium ion batteries have recently become more popular, and their specific energies are in the 90 Whr/kg range, with typical cell voltages of 3.6 V. Nickel metal hydride (NiMH) batteries are also popular, with specific energies slightly greater than those of NiCd batteries, with very similar cell voltages.
A typical portable device has an acceptable weight range between 4–12 oz. for most handheld applications based on human factors studies [33]. Assuming that battery weight is restricted to less than 50 percent of the total device weight implies an upper limit on stored energy of approximately 10 Whr for the foreseeable future. How does this limit compare to the energy requirements of a typical cellular telephone today?
Early studies of energy usage show that typical personal communicators spend only a short amount of time -- 1 hr/24 hr day -- in talk mode, where the power dissipation is at its highest [34]. Another 2 hr is spent in listen mode, and another 3 hr in standby mode. During talk time, the RF power amplifier is transmitting roughly 600 mW of power to the antenna, but draws nearly 2.5 W from the battery due to its relatively low efficiency. The power drawn by the rest of the RF portion of the device is approximately 500 mW during standby mode, so the total power dissipated by the RF portion of the device is approximately 5 Whr -- roughly 50 percent of the total energy available from the battery. As an example, a recently announced fully monolithic DECT receiver dissipated approximately 200 mW, of which 40 mW was consumed by the LNAs, 50 mW by the mixer/downconverter section, and the remaining 100 mW by the analog-to-digital converters and baseband filters [10].
This simple analysis points to several different possible areas for improvement in battery life over the next decade. These improvements include improved power amplifier power-added efficiency, reduced power dissipation for the LNA/downconverter/upconverter portions of the transceiver, and migration to microcell and picocell architectures to reduce transmitted power requirements. These first two options were explored extensively in the previous section, and the latter approach will be developed in the next section.

Network Management Issues for Improved Low-Power RF Transceiver Performance

The previous section demonstrated that the strict limitations imposed by the relatively low energy density of modern battery technology create a problem if battery life is to be significantly extended in the coming years. improvements in power amplifier efficiency and upconverter/downconverter performance will certainly improve the situation, but improvements are also required in the design and management of wireless networks in order to improve and significantly extend battery lifetimes for handheld applications.
One of the key requirements for extended battery life is the extension of the cellular environment to microcells and picocells in high-density areas [35]. Smaller cell sizes inevitably lead to lower transmitted power, and hence lower power dissipation during talk times. In addition, the performance requirements on the receiver LNA are also greatly reduced. There appears to be no fundamental lower limit to handset power dissipation as cell sizes continue to shrink. An excellent example of this approach is the Japanese personal handyphone system (PHS). It was launched in July 1995, and by the end of summer 1996 there were over 3 million subscribers. The cost for a 3 min call is roughly 10 cents, and the typical handsets have a 6 hr talk time and 200 hr standby time -- a vast improvement over cellular telephones in the United States. This increase in talk time results from the microcellular environment, which reduces transmitted power from 600 mW for an AMPS telephone to approximately 80 mW in the case of PHS.
In the limiting case, personal communications networks could be limited to a distance of a few dozen feet, and transmitted powers could be less than 1 mW. An example of such a system is the BBN BodyLAN™ project, where the portable communication device is intended to be worn, and communicates at rates of up to 90 kbytes/s over a range of 6–10 ft [36] are expected. The static power dissipation of the device is intended to be approximately 10 ΅W, with an energy dissipation of 10 nJ/b.
Other refinements are possible, and are being actively explored for improvements in the power dissipation of the radio portion of the portable communications device. First, and most obvious, are active power management techniques, whereby the dc power delivered to the device depends on its performance requirements at any given time. All of the critical devices are either turned off when not needed or powered down to achieve a lower power dissipation when the best performance is not required.
This is done today for power amplifiers, where the transmitted power is updated on a continuous basis to maintain a constant signal-to-noise ratio at the receiver. Further improvements in power management techniques are also possible. LNAs can be powered down under conditions where the absolute lowest NF is not required. VCOs could also be operated at lower powers in cases where reciprocal mixing due to strong interference is not an issue. These conditions can all be determined in the digital signal processing portion of the transceiver, and the radio circuits can be altered under computer control. Other areas of possible improvement include continuous variation in data rates to minimize dc power dissipation [37] and networking protocol variations to minimize dissipated dc power [38]. Motorola has extended the battery life of their FLEX pagers significantly through the use of improved protocols [39]. In this case, the intermittent receiving ratio -- a measure of the percentage of time required in listen mode -- dropped from 1:6.4 in the popular POCSAG system to 1:112. This allowed for a dramatic drop in the dc power dissipation of the device. A receive-only system like a pager is admittedly a special case, but this does demonstrate how improvements in the network layer can improve overall battery life.

Conclusions

The revolution in personal communications brought on by the cellular telephone is expected to be extended in coming years into the areas of wider bandwidth, Internet access, and video on demand. At the same time, the battery life of these new devices needs to be extended, from several hours today to several weeks in the future. This improvement in performance will come from developments in networking, integrated circuit technology, and radio frequency technology. Improvements in radio frequency power dissipation will be accomplished by continuing and relentless improvements in integrated circuit technology, combined with improved circuit techniques and a move to microcellular and picocellular networks.

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Biography
 Lawrence E. Larson received a B.S. degree in electrical engineering in 1979 and an M. Eng. degree in 1980, both from Cornell University, Ithaca, New York. He received a Ph.D. degree in electrical engineering from the University of California, Los Angeles in 1986. He joined Hughes Research Laboratories, Malibu, California, in 1980, where he directed work on high-frequency InP, GaAs, and silicon integrated circuit development for a variety of radar and communications applications. While at Hughes he led the team that developed the first MEMS-based circuits for RF and microwave applications. He was also assistant program manager of the Hughes/DARPA MIMIC Program from 1992–1994. From 1994–1996, he was at Hughes Network Systems in Germantown, Maryland, where he directed the development of radio frequency integrated circuits for wireless communications applications. He joined the faculty at the University of California, San Diego, in 1996, where he is the inaugural holder of the Communications Industry Chair. He was co-recipient of the 1996 Lawrence A. Hyland Patent Award of Hughes Electronics for his work on low-noise millimeterwave HEMTs. He has published over 90 papers and has received 19 U.S. patents.