Fully Monolithic CMOS RF Power Amplifiers: Recent Advances

where P_rf,out is the RF output power, P_rf,in is the RF input power, and P_dc is the total power drawn from the dc supply, or battery.
In this class of PAs, the transistor acts as a current source. A simplifying assumption may be made that the drain current waveform may be modeled as a sine wave of amplitude I_m and with a dc component I_dq. Note that I_dq will be negative for Class C, zero for Class B, and positive for Class AB or A operation. The drain current can then be written as

where y is the fraction of the RF cycle for which the transistor is on. The Fourier series expansion of this waveform is given by

where

and

The dc component of this drain current can be used to calculate the average power drawn from the power supply. With an appropriately designed load network, only the fundamental component of the drain current will flow through the load resistor. The load network will provide an alternate path for the harmonic components of current to flow. Similarly, the inductor connected to the drain of the transistor provides a path for the dc component of the drain current, and offers high impedance to the signal current. Thus, with a sinusoidal fundamental frequency current flowing through the load resistor, a sinusoidal voltage is obtained at the output.
In order to obtain the maximum voltage swing at the drain of the transistor, a suitable value of load resistance has to be presented to the device. For a given conduction angle y, the product of the load resistance presented to the device (R_opt) and the peak instantaneous value of the fundamental component of drain current (which flows through the actual load to generate the output voltage) should equal the desired voltage swing. For each value of the conduction angle, the value of R_opt will be different and can be obtained from the following constraint (the MOS field effect transistor, MOSFET, saturation voltage is denoted V_dsat):

V_dd – V_dsat = i₁(y) x R_opt (6)

where i₁ is the amplitude of the fundamental frequency current. Given the above, the efficiency of this class of power amplifiers is

Figure 4 shows a plot of the efficiency of the PAs as a function of conduction angle. As can be seen from this figure, the efficiency of the PA operating in Class C mode increases as the conduction angle decreases. Also evident is the Class A efficiency of 50 percent and Class B efficiency of 78.5 percent (neglecting V_dsat) corresponding to a conduction angle of 360° and 180°, respectively. Noteworthy in the above analysis is the implicit assumption that the output voltage swing is maximum for all values of the conduction angle. In order to meet this criterion, the load resistance value has to be different for each value of the conduction angle. Thus, this curve does not correspond to how such a PA, with a fixed load resistor, would behave if the conduction angle of the driver transistor were varied. It does, however, give an upper limit for the efficiency achievable for a fixed optimum load resistance value. This efficiency is achieved for a particular conduction angle value only, corresponding to that for which the output voltage swing is maximum.
The improvement in efficiency of these types of PAs at reduced conduction angle values is achieved at the expense of reduced power output from the PA. In fact, even though one can design a Class C PA to achieve an efficiency approaching 100 percent (as Fig. 4 suggests), the output power obtainable at this level of efficiency approaches zero. The output power obtainable from the PA is

As this indicates, the increase in efficiency (obtained by reducing the conduction angle) is achieved at the expense of reduced output power from the PA. Thus, there is a direct trade-off between the efficiency and power output in the design of this class of PAs. Similarly, as the conduction angle reduces, the harmonic content in the signal also increases, suggesting a linearity–power output–efficiency trade-off. In general, the load network for Class C PAs also acts to filter out some of the harmonics in the drain current waveform.

Design Issues for Integrated RF Power Amplifiers

Commercial RFICs are being implemented in GaAs as well as silicon (bipolar, BiCMOS, SiGe, etc.) technologies today. In recent years, application of digital CMOS technology for RFICs has emerged as a strong research area. Modern sub-micron digital CMOS processes have demonstrated f_T from several to tens of gigahertz, implying that CMOS circuits working at 1–2 GHz and above are feasible. Digital CMOS technology offers low cost and a higher degree of integration than other technologies, and opens up the possibility of a single-chip radio. However, there are some hurdles which need to be overcome before CMOS RFICs make a strong presence in the market. In contrast to the semi-insulating GaAs substrate, a highly doped substrate is common in CMOS. This results in the realization of poor-quality passive elements. Substrate interaction in a highly integrated CMOS IC also poses a significant challenge to RF CMOS. Conventional transistor models for CMOS have been found to be moderately accurate for RFICs, and need to be improved for analog operation at RF frequencies. Large-signal CMOS RF models are critical to the successful design and operation of integrated CMOS RF power amplifiers.
Due to the metal/substrate properties of CMOS processes, inductors integrated in digital CMOS exhibit high loss, and consequently have a significant impact on the performance of integrated PAs. These inductors are part of integrated input, interstage, and output matching networks in PA implementations. Accurate modeling of such inductors is critical to the design and overall performance of PAs. In addition, the parasitics associated with the device, package, and bond-wire also have a big impact on PA power output and efficiency. For example, a 1 nH package pin inductance, at 2.4 GHz, corresponds to a reactance of 15 , and ignoring this reactance will result in a poorly designed output matching network. Ground bounce is also a critical performance-limiting factor for high-power PAs. Ground bounce results due to the ground plane having a finite inductance associated with it, which assumes a significant role at RF frequencies. While inductance associated with the source (or emitter) of transistors is sometimes used in providing an input 50 match to the amplifier, it should be minimized in the high-power stages of a PA because it degrades the efficiency of and available power from the amplifier.
The above factors are the primary challenges in realizing fully integrated RF power amplifiers. Traditionally, PAs have been implemented as discretes or hybrids. RF power devices are available from a number of commercial semiconductor manufacturers which may be used to realize discrete PAs. For example, a wide variety of lateral diffused MOS (LDMOS) PA transistors, as well as PA modules based on LDMOS transistors are available from Motorola. MRF9745T1 is an LDMOS power FET available from Motorola [4] in a surface mount package which is capable of supplying greater than 1 W at 900 MHz with 55 percent drain efficiency from a 5.8 V power supply. It has a power gain of 10 dB. Similarly, MXR9745T1 and MXR9745RT1 are LDMOS power transistors capable of supplying 1.4 W power at 900 MHz with a 60 percent drain efficiency and 8.5 dB power gain from a 6 V power supply. The design of a discrete/hybrid PA involves selecting an appropriate device which meets the output power requirements at the given supply voltage and operating frequency, determining the optimum input and output impedance for the device using tuners (or load pull), and implementing matching networks using discrete inductors and capacitors to transform the 50 or 75 load (corresponding to the impedance of standard coaxial cables, antennae, RF measuring equipment, etc.) to the desired impedance values. The impact of the package parasitics, as well as parasitics associated with discrete inductors and capacitors, is incorporated into the design of discrete PAs by tuning the PA on the test bench. Indeed, it would not be an exaggeration to state that the most significant part of the design of a discrete/hybrid power amplifier is performed on the test bench.
With the obvious advantages associated with realizing highly integrated PAs, several implementations have appeared in literature with the goal of attempting to achieve PA implementations which are either low- cost, or highly integrated, or both. Figure 5 shows a GaAs MESFET implementation of a Class E PA, with a Class F driver, described in [5]. This nonlinear power amplifier outputs 250 mW at 835 MHz with a power-added efficiency of 50 percent, and operates from a 2.5 V power supply. Bias voltages are provided externally. However, this amplifier has a high degree of integration, with all the matching networks also being implemented on chip. The integrated output matching network reduces the efficiency from 75 percent (for an off-chip matching network) to 50 percent. The availability of low-loss passives in GaAs technology opens the possibility that the reduction in efficiency in the integrated PA implementation may be minimized by optimization of the design of the output matching network, in the presence of both the transistor as well as inductor and capacitor parasitics. A computer-aided design (CAD) tool which accomplishes this is used in [6], and is described in more detail later in this article.
A 1 W BiCMOS power amplifier is reported in [7]. This 830 MHz PA has a measured PAE of 30 percent, and operates from a 5 V power supply. While biasing for the different stages is provided on chip, the matching networks are not completely integrated. External inductors are used as part of interstage matching networks, with the output matching network being completely off-chip. Measurement results are reported for a chip-on-board die. The process used for this PA is a high-speed BiCMOS process from Philips Semiconductor. While BiCMOS is capable of supporting other RF transceiver functions and is a strong candidate for a low-cost technology for realizing a single-chip radio, the reduction in performance of a BiCMOS PA compared to a GaAs implementation is clearly evident.
As stated earlier, due to the high volume of digital ICs using CMOS technology, digital CMOS is an extremely attractive candidate for realizing low-cost RF circuits. However, this process is geared toward optimizing digital circuit performance which imposes severe restrictions on realizing high-performance RF circuits in this technology. Any process modifications aimed at improving RF circuit performance tend to increase cost, thereby reducing the primary advantage of digital CMOS over other RF technologies. However, CMOS PAs have been reported recently [6, 8, 9]. A balanced 20 µW–20 mW 900 MHz CMOS power amplifier is described in [8]. It works from a 3 V power supply, and has a measured drain efficiency of 25 percent. No input matching is used (an input matching network is not required if the PA is integrated with the remaining transmitter circuitry), and the output matching network is off-chip. Process modifications are used to obtain a high Q inductor for realizing a tuned amplifier to drive the PA output stage. This PA is realized in a 1 µm CMOS technology. Figure 6 shows a 2.5 V, 1 W CMOS PA for operation in the 800–900 MHz band as described in [9]. The final stage of this multistage amplifier is implemented with the transistor used as a switch. This amplifier has a measured drain efficiency of 62 percent and a PAE of 42 percent, but does not have a high degree of integration, with the input and output matching network being off-chip. Bond wires are also used as part of the interstage matching networks. This PA, however, does indicate that even though the inductors and capacitors that may be realized in CMOS technology are not suitable for RF circuits requiring high performance, CMOS transistors do have adequate gain at 1 GHz to allow the design of low-cost hybrid (not monolithic) 1 W amplifiers. Of course, the performance is still not comparable to GaAs or LDMOS, but the advantage is in the cost of implementation.
While advances have been made in realizing PAs in low-cost technologies, the issues mentioned at the beginning of this section have prevented the realization of fully integrated CMOS (or BiCMOS) PAs. A CAD tool is used in [6] to overcome some of these hurdles. This tool has been developed to optimize/design PAs for operation at maximum efficiency in the presence of parasitics associated with on-chip active and passive elements. With the goal of a completely integrated PA in mind, a simple but realistic model for planar inductors fabricated on silicon is made part of this CAD tool. Figure 7 shows the 100 mW, 3 V, 900 MHz balanced Class AB PA described in [6]. This PA is completely integrated, and has displayed a measured drain efficiency of 50 percent while supplying 100 mW into a 50 W load. The CAD tool is based on the simulated annealing heuristic and is used to determine the optimum load impedance to be presented to the device as well as to design an appropriate matching network using integrated inductors and capacitors (similar to tuning the PA on the test bench). Figure 8 shows the flow diagram of this CAD tool.

Conclusions

This article attempts to provide the reader with a basic understanding of the operation of a particular class of RF power amplifiers -- Class A, B and C PAs. It highlights some of the key issues in the design of such power amplifiers, and gives examples of the current state of the art in PA implementations as well as research trends in the design of fully integrated power amplifiers in low-cost CMOS or BiCMOS processes. While advances have been made in the efficient realization of integrated PAs, there is a strong continuing effort to achieve higher degrees of integration without sacrificing cost or performance.

References
[1] P. R. Gray, "Architectures and Technologies for CMOS RF Transceivers," Short Course on RF CMOS Circuit Design for Pers. Commun. Sys., IEEE Int'l. Solid-State Circuits Conf., 1997.
[2] T. S. Rappaport, Wireless Communications: Principles and Practices, Piscataway, NJ: Prentice Hall PTR, 1996.
[3] H. L. Krauss, C. W. Bostian, and F. H. Raab, Solid State Radio Engineering, New York: Wiley, 1980.
[4] http://mot-sps.com/sps/General/chips-nav.html
[5] T. Sowlati et al., "Low Voltage, High Efficiency GaAs Class E Power Amplifiers for Wireless Transmitters," IEEE J. Solid-State Circuits, Oct. 1995, pp. 1074–79.
[6] R. Gupta and D. J. Allstot, "Parasitic-Aware Design and Optimization of CMOS RF Integrated Circuits," IEEE RFIC Symp., June 1998, pp. 325–28.
[7] S. L. Wong et al., "A 1W 830MHz Monolithic BiCMOS Power Amplifier," IEEE Int'l. Solid-State Circuits Conf., 1996, pp. 52–53.
[8] M. Rofougaran et al., "A 900 MHz CMOS RF Power Amplifier with Programmable Output," Symp. VLSI Circuits, 1994, pp. 133–34.
[9] D. Su and W. McFarland, "A 2.5V, 1-W monolithic CMOS RF Power Amplifier," Custom Integrated Circuits Conf., 1997, pp. 189–93.

Biographies
Ravi Gupta received a B.E. from Delhi College of Engineering, India, in 1991, an M.S.E.E. from the University of Pittsburgh in 1993, and a Ph.D. from Oregon State University in 1998. In 1997 he interned with Motorola, Inc., designing upconverters and power amplifiers for radios. Since July 1998 he has been with Maxim Integrated Products, Inc., where he is designing front-end ICs for wireless products.
David J. Allstot [F] received a B.S. from the University of Portland, an M.S.E.E. from Oregon State University, and a Ph.D. from the University of California, Berkeley. He previously held industrial positions with Tektronix and Texas Instruments, and academic positions with Oregon State and Carnegie Mellon Universities. He is currently professor of electrical engineering at Arizona State University. He has received several teaching and outstanding paper awards.