CALL FOR PAPERS
IEEE JSAC Special Issue on Channel Modeling, Coding and Signal Processing for Novel Physical Memory Devices and Systems
Advancements in the theoretical foundations from 70 plus years of signal, information and communication theories have been used with phenomenal success in data storage systems starting from punch cards to today’s sophisticated memory devices. However, existing approaches designed for simpler channels do not meet the needs of new storage technologies where the data must be packed densely in two and higher dimensions with various read, write and media conditions. This requires a fundamental understanding into the channel characterization under adverse physical constraints, information-theoretic limits for storage and practical ways for getting to the storage limits by novel signal processing and coding techniques.
At the device level, recent advances in data storage technologies, such as 3D non-volatile memories (NVM), shingled and two-dimensional magnetic recording (SMR and TDMR) and energy-assisted magnetic recording (HAMR) are bound to transform the storage industry in the next few years. These technologies require the information to be stored and accessed in higher dimensions. Also, emerging technologies such as STT RAMs, phase change memories, memristors etc. are bound to transform the future of data storage. At the system level, we need new architectures catering to high throughput and better energy efficiencies with lower cost for realizing and integrating the Silicon architectures into the memory hierarchy.
The possible topics include, but are not limited to:
- Novel aspects of read, write and media characterization for emerging physical memories • Channel modeling for emerging storage technologies such as STT RAMs, memristors etc.
- Analysis of novel recording paradigms and performance evaluation
- Information theoretic limits for storage over new physical memory channels
- Practical coding methods cognizant of underlying physical constraints
- Innovative signal processing algorithms for analog front end, synchronization, equalization and detection for emerging storage technologies
- Architecture and design of coding and signal processing subsystems for new non-volatile memories, magnetic and optical memories
- Practical coding methods cognizant of underlying physical constraints, parallelizable coding algorithms for higher throughput
Original, previously unpublished research articles will be considered. Authors should follow the IEEE JSAC manuscript format described in the Information for Authors, which can be found at http://www.comsoc.org/jsac/author-information. Papers should be submitted through EDAS (http://www.edas.info) according to the following schedule:
Manuscript submission: April 15, 2016 Extended to May 2, 2016
Acceptance notification: July 15, 2016
Final manuscript: August 8, 2016
Publication: Third quarter of 2016
Shayan Garani Srinivasa (IISc), Tong Zhang (RPI), Ravi Motwani (Intel Corporation), Haralampos Pozidis (IBM Zurich) and Bane Vasic (UA), Muriel Medard (Editor-in-Chief)