Jin Liu and Hlaing Minn, Guest Editors
Alan Gatherer, Editor in Chief, ComSoc Technology News
Editor's note: While we are on the topic of things that might kill 5G, or at least cause it to evolve into something other than we think it is today, I think the topic of the analog front-end of massive MIMO is worth a closer look. So many papers side-step this issue with a note that analog beam forming solutions will solve the problem. Though some very interesting work has been done in this area, this sounds like a punt down the field to me. History has taught us that analog never replaces digital for all that long. In order to step back and cast an impartial eye on the problem I recently drove down the road from my office in, what at that time was, a quite soggy Plano TX to an equally soggy Richardson and the home of UT Dallas. Below is the result of this effort; a nice little summary by Professors Liu and Minn on some of the issues that face ADC development if we are to implement 5G massive MIMO in production. I'm sure there are more issues than mentioned here and comments are always welcome.
Analog Front End Design Challenges for 5G Massive MIMO
Jin Liu and Hlaing Minn
The exponential growth of data rate has led to the demand for 5G wireless systems with an expected data bandwidth of several GHz and carrier frequencies in the millimeter wave range (tens of GHz to 100GHz) [1-5]. Due to large propagation losses at this frequency range, beamforming with massive MIMO plays a central role in establishing reliable communication links. It is expected that the required number of antennas will be an order of magnitude larger than existing wireless systems. This presents significant challenges in the analog front end design.
Most of the current beamforming techniques for existing wireless systems operate in the digital baseband domain and enjoy flexibility, adaptability, and performance optimality. These digital beamforming techniques require an ADC unit for each receiver antenna. The large number of antennas anticipated in millimeter wave beamforming presents several challenges such as: high power consumption, the high cost of a large number of ADCs operating at very high sampling frequencies (possibly several GS/s to 100GS/s), difficulty in wiring high speed signals in the millimeter wave range between the antennas and the ADCs, and bulky transceiver devices (cell phones/base station) requiring increased cost and power consumption. There do exist analog beamforming techniques operating in the RF domain, that require a much fewer number of baseband ADCs. Although this is advantageous from the ADC power and cost perspective, complete analog beamforming lacks flexibility/adaptability, sacrifices the overall system performance and presents tremendous challenges and reliability issues in hardware design for millimeter wave carrier signals. An interesting direction to pursue is a hybrid between analog and digital beamforming methods. This might potentially be a compromise to reduce the number of ADCs and to improve system performance and flexibility.
High-performance and high-speed ADCs have become critically important for future massive MIMO in 5G wireless systems. Historically, high-speed ADC design has been driven by wireline applications with ADC sampling rates of 40 to 100GS/s and a low resolution of about 6 bits, as well as wireless applications such as base station receivers with ADC sampling rates of 1- 5GS/s and medium resolution of around 10 bits. The state-of-the-art, high-speed, medium resolution ADC has a sampling rate of approximately 5GS/s, an effective resolution of approximately 9 bits and consumes around 500mW. For future 5G wireless systems, which will have a significantly larger bandwidth than current systems, a much higher ADC sampling speed is needed. The ADC resolution can still remain around 10 bits if current modulation schemes are used. But, because there will be several distinctive differences between 5G and current wireless systems, the actual required resolution is not known. Because 5G will operate in the millimeter wave frequency range with a very short propagation distance, these systems will need a large number of antennas and consequently a large number of ADCs. Therefore, the ADC power consumption is also a critical concern. In summary, the limited sampling speed and high power consumption of current ADCs are among the key bottleneck issues for future 5G wireless systems.
The requirements for ADC sampling speed and resolution depend on the type of beamforming solution. In addition, the demodulation method at the receiver determines the required ADC sampling speed. If ADCs are used to directly sample the carrier frequency, the required ADC sampling speed should be relatively high. Sub-sampling can be considered to lower the ADC sampling speed, but this requires spectrum folding which requires sophisticated filtering and hence higher ADC resolution. If the ADCs are used to sample at the intermediate frequency (IF) stage, the required sampling speed will be lower, but, additional hardware is required to convert the signal to the IF frequency range. Direct conversion of the signal from the IF to the base band will further reduce the required ADC sampling speed, but might suffer issues such as in-phase and quadrature imbalance.
In particular for wireless applications, it is generally preferred that the ADC has a large spurious free dynamic range (SFDR). This can be a significant challenge for high-speed ADC design, as most high-speed ADCs with sampling rates around 10GS/s use the time-interleaving technique. For example, the overall ADC speed in  is 10GS/s and it is realized with four time-interleaving channels with each of the four channels running at 2.5GS/s. Each channel is clocked by one of the 2.5GHz four-phase clocks. Without careful calibration, there is always timing skew among the clocks for the interleaving channels. The timing skew can cause significant spurs in the spectrum reducing the SFDR value. For example, before the skew calibration in , there exists a large spur of -26.8dB at fs/2-fin, where fs is the sampling frequency of 10GHz and fin is the input frequency close to 5GHz, corresponding to about 3ps time skew. After the skew calibration , it is reduced to -48.4dB, corresponding to about 0.25ps time skew. The SFDR is improved by about 20dB as a result. The SFDR requirement indicates that the ADC structure cannot use a large number of time interleaving channels.
Current high-speed CMOS ADCs have been realized by time-interleaving pipeline, Successive Approximation and flash architectures. As we venture into future 5G wireless systems, the ADC specification matrix has become more challenging. An additional issue to address is the ADC metastability error rate at high speeds requiring increased signal bandwidth and large SFDR requirements. Based on these hardware issues, it is essential that we revisit the general design methodology and fundamental architecture perspectives of the ADC design to meet the challenging performance specifications of 5G wireless communications.
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